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Da ta S he et , V 1. 3, O ct . 20 03
T C 1 92 0
3 2 - B i t S i n g le - C h i p M ic r o c o n t r o l l e r
M i c ro c o n t ro l l e rs
Never
stop
thinking.
Edition 2003-10 Published by Infineon Technologies AG, St.-Martin-Strasse 53, D-81541 Munchen, Germany (c) Infineon Technologies AG 2003. All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Da ta S he et , V 1. 3, O ct . 20 03
T C 1 92 0
3 2 - B i t S i n g le - C h i p M ic r o c o n t r o l l e r
M i c ro c o n t ro l l e rs
Never
stop
thinking.
TC1920 Preliminary Revision History: Previous Version: Page
2003-10 1.2
V 1.3
Subjects (major changes since last revision) ASC and SSC baudrates calculated for 50 MHz DC parameters updated with characterization values AC parameters updated with characterization values
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TC1920
Preliminary TC1920 Features The TC1920 offers a 32 bit TriCore based microcontroller/DSP, which is mainly designed for automotive telematics applications. Due to its high integration, this microcontroller/ DSP offers high system performance at minimized cost. Typical telematics functions processed by RISC-, DSP- and speech- (CODEC) modules are now combined in one component. The combination of dedicated automotive peripherals (CAN, J1850) and standard peripherals (ADC, SSC/SPI, ASC and IIC), makes this microcontroller/DSP the engine tailored for a wide variety of telematics applications such as navigation, emergency call, speech interface or communication interface. * TriCore CPU/DSP with 4-Stage Pipeline: - 100 MHz max. CPU clock frequency, 50 MHz max. FPI Bus clock frequency. - 32-bit super-scalar TriCore main CPU - 4-GByte unified memory space support - Fast context-switching - Dual 16 x 16 Multiply-Accumulate (MAC) Unit - 64-bit Local Memory Bus (LMB) - 32-bit Flexible Peripheral Interface (FPI) - 32-bit wide external bus unit (EBU) * 32-bit Peripheral Control Processor (PCP2) with DMA-support * On-chip memories: - 24 KByte Code Scratch-Pad RAM (CSRAM) - 8 KByte Instruction Cache (ICACHE) - 24 KByte Data Scratch-Pad RAM (DSRAM) - 8 KByte Data Cache (DCACHE) - 64 KByte fast LMB SRAM - 16 KByte FPI SRAM (of which 8 KByte Stand-By SRAM) - 20 KByte PCP RAM: 16 KByte Code and 4 KByte Data SRAM - 32 KByte Boot ROM * Product Specific Peripherals: - 14-bit double CODEC with flexible sample rates and FIFO support * Automotive Peripherals: - Two independent CAN-nodes (TwinCAN) with gateway support - J1850 (SDLM) * Standard Peripherals: - 6-channel, 8-/10-/12-bit ADC - 3 x asynchronous serial interface (ASC) with IrDa-support - 1 SPI-compatible synchronous serial interface - 2-channel IIC - 6 x 32 bit timer - 16 I/O- and interrupt pins (GPIO) * General Peripherals: - Real time clock (RTC)
Data Sheet 1 V 1.3, 2003-10
TC1920
Preliminary * * * * * * - Watchdog timer (WDT) Clock Generation Unit with PLL Debug Support: - Debug Interface (OCDS level 2) with Trace Port Power saving features Dual voltage supply (1.8V core, 3.3V I/O) -40C to +85C temperature range LBGA-260 package
Data Sheet
2
V 1.3, 2003-10
TC1920
Preliminary Block Diagram The figure below shows the block diagram of the TC1920 device.
LFI Bridge ADC
SRAM 64 kB
EBU
3 2 b it E xte rn a l M em ory B u s
6 4 -b it Lo ca l M em o ry B us (L M B )
ASC0
CO DEC PM U 24 K B CSRAM 8KB IC A C H E
MMU TriCore (T C 1 .3 ) C PS DM U 24 K B DSRAM 8K B DCACHE
ASC1
G PTU0
ASC2
G PTU1
SSC
Port Control
OCD S Debug Interface /JTAG
IIC PCO DE 1 6kB PCP2 PRAM 4kB
Tw in CAN
F P I-B u s Inte rface J1850
32 -bit F le xible P e rip h e ra l In te rface (F P I)B u s
Boot RO M 32kB
SRAM 16 kB
R TC
STM
SCU
TC1920
Figure 1
TC1920 Device Block Diagram
Data Sheet
3
V 1.3, 2003-10
TC1920
Preliminary Target applications * * * * * * * * * On-board and off-board navigation Emergency call systems Car speech interface Car communication interface Gateways: automotive - infotainment Occupant Sensing Drowsiness detection Rear- & side-mirror replacement Pre-crash sensing
Logical Symbol
A lte rn a te F u n ctio ns
P LL _C T R L TEST G e ne ral C on trol CLKOUT HDRST PORST NMI BYPASS XTAL1 XTAL2 XTAL3 XTAL4 VD D O SC 1 O scillators PLL VSS O SC 1 VD D O SC 2 VSS O SC 2 VD D P LL VSS PL L VD D D igita l C irc uitry P o w e r S u p p ly VD D P V D DS B VSS VD D A V D D_ C O D 0 V SS _C O D 0 V D D_ C O D 1 V SS _C O D 1 V R EF_ CO D V G N D _C O D CO DEC A na lo g P o w er S u pp ly 16 P o rt 5 8 G P IO / T rac e TC 1920 10 C O D E C 0/1 6 ADC P o rt 0 8-b it P o rt 1 8-bit P o rt 2 16 -bit P ort 3 1 6-b it G P IO /E X Ix , Codec Bypass
G P IO / G PTU1 CAN0/1 / J1850 / SSC A S C 0 / IIC
A S C 1 /2 / A D C M U X A D C E X T IN / G P T U 0
83 E x tern al B us In terface
O C D S /JT A G C on trol
A D C A nalog Pow er S upply
VS SA V AR E F VAG N D
Figure 2
Logical Symbol of the TC1920 Device
Data Sheet
4
V 1.3, 2003-10
TC1920
Preliminary Pin Configuration
1 A B C D E F G H J K L M N P R T U V V SS AD 31
2 V DDR
3
4
5
6
7
8 V SS_
GUARD P LL C T R L _A0
9 P 4 .5 V SS _
P LL
10 P 4 .3 P 4 .2 P 4 .4
11 P 4 .1
12 V SS A_
ADC
13 A I0 -
14 A I1 A O1 AO1+ A I1 +
15 AO+ AO-
16 VDD VDD
17 CEXT
18 NMI A
TM_ V SS P VDD_ C T R L 1 X T A L 3 _ O S C X TA L 1 O S C 1 VDD TM_ V S S_ C T R L 0 X TA L4 O S C X T A L 2 V DD VDD R VDD VDD_
OS C2
V SS
V A G N D _ V S S P _ V R E F_
A DC ADC COD
BY PORS B T PASS P 2 .1 1 C D E F G H J K L M N P R T U V
AD 27 AD 30
V SS
V DDP_
OSC
V SS_
GUARD
VDD_
GUARD
P 4 .0
V DD P_ V GND_
ADC COD
V SSP_ C O D E C LK C O D 0 C _ D IS O U T
AD 26 AD 28 A D 29
VSS
V SS
V D D P _ V S S P _ V D D _ V S S P _ V A R E F_ V S S P _
OSC OSC P LL A DC A DC ADC
A I0 +
V SSA_ H R S T P 2 .13 P 2 .1 0
COD0
AD 23 AD 24 A D 25 AD 18 AD 19 AD 20 A D 22 AD 21 AD 13 AD 14 A D 15 AD 17 AD 10 AD 11 A D 12 AD 16 AD8 AD6 AD4 AD9 AD5 AD1 AD7 AD2 AD0 V DD AD3 V DD A 22 A 21 A 19 V DD A4 RD BC2 4 A12 A1 RAS CS5 5 BC1 CAS BC3 CS4 6 CS2 BC0 CS6 CS3 7 CS1 W A IT BAA CS0 CS OVL CS GLB ADV A LE CKE P 5 .9 P 5 .1 2 P 5 .8 P 5 .7 P 5 .5 P 5 .2 P 5 .6 P 5 .3 BRK OU T V DDP V DDP VDDP
V DDP_
COD0
P 2 .1 4
P 2 .8 P 2 .5 P 2 .1
P 2 .4 P 2 .3 P 2 .0
P 2 .1 5 P 2 .1 2
V SS V SS V SS V SS V SS V SS
V SS V SS V SS V SS V SS V SS
V DDP
VDDP VDDP
P 2 .9 P 2 .6
P 2 .7 P 2 .2
VSS VSS VSS VSS
VDDP
V SS V SS V SS V SS
V DDP
P 3 .14 P 3 .1 3 P 3 .9 P 3 .8 P 3 .6 P 3 .3 P 0 .5 P 0 .4 P 0 .0 P 1 .6 P 1 .4 P 1 .0 18
V SS V SS
V DDP V DDP
VSS VSS
VDDP VDDP
P 3 .1 2 P 3 .1 5 P 3 .11 SCAN M O D E P 3 .1 0 P 3 .0 P 0 .7 P 0 .6 P 0 .3 VDD_
SB
P 3 .7 P 3 .4 P 3 .2 P 0 .2 P 1 .7 P 1 .5 P 1 .3 TR S T TDI 17
P 3 .5 P 3 .1 P 0 .1 P 1 .2 P 1 .1 TCK
EBU BFC LK A 20 C LK 0 A23 A17 A16 A10 A7 A2 1 A18 A14 A13 A9 A5 A0 2 A 15 A 11 A8 A6 A3 RD/ WR 3
TMS
P 5 .1 4 P 5 .1 1
P 5 .1 B R K IN T D O P 5 .4 14 P 5 .0 15 OC D SE 16
CS CM M R /W P 5 .1 5 P 5 .1 3 P 5 .1 0 EMU D ELAY 8 9 10 11 12 13
T O P V IE W
LB G A 260
Figure 3
TC1920 Pinning
Data Sheet
5
V 1.3, 2003-10
TC1920
Preliminary Pin List Table 1 Symbol Pin Definitions and Functions Pad1) BGA In/ Functions BALL Out2) External Bus Unit interface external address/data bus (multiplexed bus mode) or data bus (demultiplexed bus mode) for the EBU: AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 274 273 272 271 270 269 268 264 263 262 261 260 259 258 253 252 251 250 249 248 247 243 242 241 240 239 238 237 232 231 230 229 L3 L2 K3 K4 L1 K2 K1 J3 J1 J2 H1 H2 H3 G1 G2 G3 H4 G4 E4 F1 F2 F4 F3 E1 E2 E3 D1 C1 D2 D3 C2 B1 I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s Address/data bus / Data bus line 0 Address/data bus / Data bus line 1 Address/data bus / Data bus line 2 Address/data bus / Data bus line 3 Address/data bus / Data bus line 4 Address/data bus / Data bus line 5 Address/data bus / Data bus line 6 Address/data bus / Data bus line 7 Address/data bus / Data bus line 8 Address/data bus / Data bus line 9 Address/data bus / Data bus line 10 Address/data bus / Data bus line 11 Address/data bus / Data bus line 12 Address/data bus / Data bus line 13 Address/data bus / Data bus line 14 Address/data bus / Data bus line 15 Address/data bus / Data bus line 16 Address/data bus / Data bus line 17 Address/data bus / Data bus line 18 Address/data bus / Data bus line 19 Address/data bus / Data bus line 20 Address/data bus / Data bus line 21 Address/data bus / Data bus line 22 Address/data bus / Data bus line 23 Address/data bus / Data bus line 24 Address/data bus / Data bus line 25 Address/data bus / Data bus line 26 Address/data bus / Data bus line 27 Address/data bus / Data bus line 28 Address/data bus / Data bus line 29 Address/data bus / Data bus line 30 Address/data bus / Data bus line 31
Data Sheet
6
V 1.3, 2003-10
TC1920
Preliminary Table 1 Symbol Pin Definitions and Functions Pad1) BGA In/ Functions 2) BALL Out External Bus Unit interface (continued) external address bus for the EBU or chip select output lines. A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 CS0 CS1 CS2 CS3 CS4 CS5 CS6 CSEMU CSOVL 9 6 5 4 3 2 307 306 303 302 301 300 299 295 294 293 292 291 290 289 285 284 283 282 28 27 26 25 24 23 22 36 37 V2 T5 V1 U3 T4 U2 T3 U1 R3 T2 T1 P3 R5 R2 P2 N3 R1 P1 N2 P4 M3 N4 M4 N1 R9 R8 R7 V7 V6 V5 U7 V8 T9 I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s I/O,s O,u O,u O,u O,u O,u O,u O,u O,u O,u Address bus line 0 Address bus line 1 Address bus line 2 Address bus line 3 Address bus line 4 Address bus line 5 Address bus line 6 Address bus line 7 Address bus line 8 Address bus line 9 Address bus line 10 Address bus line 11 Address bus line 12 Address bus line 13 Address bus line 14 Address bus line 15 Address bus line 16 Address bus line 17 Address bus line 18 Address bus line 19 Address bus line 20 Address bus line 21 Address bus line 22 Address bus line 23 Chip select output 0 Chip select output 1 Chip select output 2 Chip select output 3 Chip select output 4 Chip select output 5 Chip select output 6 Chip select for emulator region Chip select for emulator overlay memory
Data Sheet
7
V 1.3, 2003-10
TC1920
Preliminary Table 1 Symbol Pin Definitions and Functions Pad1) BGA In/ Functions 2) BALL Out External Bus Unit interface (continued) control bus for the EBU control lines. RD RD/WR ALE ADV BC0 BC1 BC2 BC3 WAIT BAA EBUCLK BFCLK0 CSGLB CMDELAY MR/W CKE RAS CAS P0 11 12 45 46 218 17 16 15 32 33 278 279 38 39 40 44 13 14 U4 V3 T10 R10 T7 R6 V4 U6 T8 U8 M1 M2 U9 V9 V10 U10 U5 T6 I/O,u I/O,u O,d O,u I/O,u I/O,u I/O,u I/O,u I/O,u O,u O,d O,d O,u I,u O,u O,d O,u O,u Read control line Write control line Address latch enable Address valid output Byte control line 0 Byte control line 1 Byte control line 2 Byte control line 3 Wait input Burst address advance output External Bus Clock Additional clock Chip Select Global Command Delay Motorola-style Read/Write Clock Enable Row Address Strobe Column Address Strobe Port 0 Port 0 serves as 8-bit general purpose I/O port, that can also be used for the codec digital signals. P0.[3:0] also serve as external interrupt inputs. 94 95 98 102 103 104 105 106 R18 N16 N17 P15 P18 N18 N15 M15 I/O I/O I/O I/O I/O I/O I/O I/O EXI0IN EXI1IN EXI2IN EXI3IN SCLK LRCK MUTE0 MUTE1 External interrupt input 0 Ext. interrupt input 1 / DATA_IN Ext. interrupt input 2 / DATA_OUT Ext. interrupt input 3 / MCLK
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
Data Sheet
8
V 1.3, 2003-10
TC1920
Preliminary Table 1 Symbol P1 Pin Definitions and Functions Pad1) BGA In/ Functions 2) BALL Out Port 1 Port 1 is an 8-bit bidirectional general purpose I/O port which is also used as input/output for the GPTU1 83 84 85 86 87 91 92 93 V18 R16 P16 T17 U18 R17 T18 P17 I/O I/O I/O I/O I/O I/O I/O I/O GPTU1.0 GPTU1.1 GPTU1.2 GPTU1.3 GPTU1.4 GPTU1.5 GPTU1.6 GPTU1.7 GPTU1 I/O line 0 GPTU1 I/O line 1 GPTU1 I/O line 2 GPTU1 I/O line 3 GPTU1 I/O line 4 GPTU1 I/O line 5 GPTU1 I/O line 6 GPTU1 I/O line 7
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 P2
Port 2 Port 2 is a 16-bit bidirectional general purpose I/O port which is also used as input/output for serial interfaces (CAN, J1850, IIC, ASC0, SSC) 131 132 133 137 138 139 140 141 142 143 147 148 149 150 151 152 G18 G17 H16 F18 E18 F17 H15 G16 E17 G15 D18 C18 F16 D17 E16 F15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O RXDCAN0 CAN 0 receiver input TXDCAN0 CAN 0 transmitter output RXDCAN1 CAN 1 receiver input TXDCAN1 CAN 1 transmitter output RXJ1850 SDLM receiver input TXJ1850 SDLM transmitter output SCL0 IIC Serial Port Clock line 0 SDA0 IIC Serial Port Data line 0 SCL1 IIC Serial Port Clock line 1 SDA1 IIC Serial Port Data line 1 RXD0 ASC0 receiver input/output TXD0 ASC0 transmitter output SCLK SSC clock line MRST SSC master receive/slave transmit MTSR SSC master transmit/slave receive PLL_CLC.LOCK Monitoring of PLL_CLC.LOCK
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 P2.8 P2.9 P2.10 P2.11 P2.12 P2.13 P2.14 P2.15
Data Sheet
9
V 1.3, 2003-10
TC1920
Preliminary Table 1 Symbol P3 Pin Definitions and Functions Pad1) BGA In/ Functions 2) BALL Out Port 3 Port 3 is a 16-bit bidirectional general purpose I/O port which is also used as input/output for serial interfaces (ASC0 and ASC1), for timer (GPTU0) and ADC control lines 107 108 109 110 115 116 117 118 119 120 124 125 126 L15 M16 M17 M18 L17 L16 L18 K17 K18 J18 K16 J17 J15 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O GPTU0.0 GPTU0.1 GPTU0.2 GPTU0.3 GPTU0.4 GPTU0.5 GPTU0.6 GPTU0.7 RXD1 TXD1 RXD2 TXD2 GPTU0 I/O line 0 GPTU0 I/O line 1 GPTU0 I/O line 2 GPTU0 I/O line 3 GPTU0 I/O line 4 GPTU0 I/O line 5 GPTU0 I/O line 6 GPTU0 I/O line 7 ASC1 receiver input/output ASC1 transmitter output ASC2 receiver input/output ASC2 transmitter output OSCBYP latch-in input ADCMUX0/EXI5IN/HWCFG0 ADC external mux control 0 / external interrupt input 5 / hardware configuration input 0 / ADCMUX1/EXI6IN/HWCFG1 ADC external mux control 1 / external interrupt input 6 / hardware configuration input 1 ADCMUX2/EXI7IN/HWCFG2 ADC external mux control 2 / external interrupt input 7/ hardware configuration input 2 ADEXTIN ADC external trigger input
P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 P3.8 P3.9 P3.10 P3.11 P3.12
P3.13
127
H18
I/O
P3.14
128
H17
I/O
P3.15
129
J16
I/O
Data Sheet
10
V 1.3, 2003-10
TC1920
Preliminary Table 1 Symbol P4 Pin Definitions and Functions Pad1) BGA In/ Functions 2) BALL Out Port 4 Port 4 provides the 6 analog input lines for the AD Converter (ADC). 190 191 192 193 194 195 C11 A11 B10 A10 C10 A9 I I I I I I AIN0 AIN1 AIN2 AIN3 AIN4 AIN5 CODEC D13 A13 A15 B15 D14 A14 C14 B14 A17 C16 I I O O I I O O I I CODEC 0 Non-Inverting Input CODEC 0 Inverting Input CODEC 0 Non-Inverting Output CODEC 0 Inverting Output CODEC 1 Non-Inverting Input CODEC 1 Inverting Input CODEC 1 Non-Inverting Output CODEC 1 Inverting Output Codec External Clock Input Codec Disable (power saving) DEBUG (OCDS/JTAG Control) 82 81 80 76 75 73 72 71 U17 T16 V17 U16 T15 V16 U15 T14 I,d I,u I,u O I,u I,u I,u O Reset/module enable JTAG clock input Serial data input Serial data output State machine control signal OCDS enable input OCDS break input OCDS break output Test pins K15 B8 B4 A3 I I I I Scan Mode Control current of different analog stages Test Mode Control 0 Test Mode Control 1
11 V 1.3, 2003-10
P4.0 P4.1 P4.2 P4.3 P4.4 P4.5 CODEC
Analog input 0 Analog input 1 Analog input 2 Analog input 3 Analog input 4 Analog input 5
180 181 169 165 176 177 170 172 162 CODEC_DIS 163 AI0+ AI0AO0+ AO0AI1+ AI1AO1+ AO1CEXT DEBUG TRST TCK TDI TDO3) TMS OCDSE BRKIN BRKOUT3) Test 114 202 TM_CTRL0 215 TM_CTRL1 216
SCAN_MODE PLLCTRL_AO
Data Sheet
TC1920
Preliminary Table 1 Symbol P5 TRACE [15:0] P5.0 P5.1 P5.2 P5.3 P5.4 P5.5 P5.6 P5.7 P5.8 P5.9 P5.10 P5.11 P5.12 P5.13 P5.14 P5.15 BYPASS NMI HRST PORST 70 69 68 67 63 62 61 60 59 58 54 53 52 51 48 47 161 160 159 158 V15 U14 T13 R14 V14 R13 U13 T12 R12 R11 V13 U12 T11 V12 U11 V11 B17 A18 D16 B18 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I,d I,u I,u Pin Definitions and Functions Pad1) BGA In/ Functions 2) BALL Out Port 5 Trace Lines to output CPU or PCP2 OCDS level 2 trace signals CPU or PCP2 trace output 0 / GPIO CPU or PCP2 trace output 1 / GPIO CPU or PCP2 trace output 2 / GPIO CPU or PCP2 trace output 3 / GPIO CPU or PCP2 trace output 4 / GPIO CPU or PCP2 trace output 5 / GPIO CPU or PCP2 trace output 6 / GPIO CPU or PCP2 trace output 7 / GPIO CPU or PCP2 trace output 8 / GPIO CPU or PCP2 trace output 9 / GPIO CPU or PCP2 trace output 10 / GPIO CPU or PCP2 trace output 11 / GPIO CPU or PCP2 trace output 12 / GPIO CPU or PCP2 trace output 13 / GPIO CPU or PCP2 trace output 14 / GPIO CPU or PCP2 trace output 15 / GPIO PLL Bypass Control Input. Non-Maskable Interrupt Input Power-on Reset Input PORST must be active during power-up of the device CPU Clock Output PLL/Oscillator Input/Output Real Time Clock Oscillator input/output (32 KHz) Main Oscillator Power Supply (1.8V) RTC Oscillator Power Supply (1.8V) RTC & Main Oscillator Ground (1.8V) RTC & Main Oscillator Power Supply (3.3V)
12 V 1.3, 2003-10
I/O,u Bidirectional Hardware Reset
CLKOUT XTAL1 XTAL2 XTAL3 XTAL4 VDD_OSC1 VDD_OSC2 VSS_OSC VDDP_OSC
Data Sheet
156 208 207 214 213 206 212 211 205
C17 A6 B7 A4 B5 A7 C6 B6 D7
O I O I O -
TC1920
Preliminary Table 1 Symbol VDDP_OSC VSSP_OSC VSSP_OSC VDD_PLL VSS_PLL VDDP_ADC VSSP_ADC VSSP_ADC VSSP_ADC VSSA_ADC VAREF_ADC VDDP_COD0 VSSA_COD0 VDDP_COD1 VSSA_COD1 VSSP_COD0 VSSP_COD1 VREF_COD VGND_COD VDDR VDDR VSS_GUARD VSS_GUARD VDD_SB VDDP
Data Sheet
Pin Definitions and Functions Pad1) 210 203 209 198 199 185 184 186 196 187 189 166 167 175 174 168 173 178 179 217 224 201 204 97
4)
BGA In/ Functions 2) BALL Out C7 D8 A5 D9 B9 C12 B12 D12 D10 A12 D11 B11 E15 D15 E15 D15 C15 C15 B13 C13 A2 C5 C9 A8 C8 R15 RTC & Main Oscillator Power Supply (3.3V) RTC & Main Oscillator Ground (3.3V) RTC & Main Oscillator Ground (3.3V) PLL Supply (1.8V) PLL Ground (1.8V) ADC Port and Analog Part Power Supply (3.3V) ADC Port and Analog Part Ground (3.3V) ADC Port and Analog Part Ground (3.3V) ADC Port and Analog Part Ground (3.3V) ADC Analog Ground (3.3V) ADC Reference Voltage ADC Reference Ground Codec 0 Port and Analog Part Power Supply (3.3V) Codec 0 Analog Ground Codec 1 Port and Analog Part Power Supply (3.3V) Codec 1 Analog Ground Codec 0 Pad Ground (3.3V) Codec 1 Pad Ground (3.3V) Codec 0,1 Reference Voltage Codec 0,1 Reference Ground Stand-By SRAM Power Supply (1.8V) Stand-By SRAM Power Supply (1.8V) Guard Ring Supply (1.8V) Guard Ring Ground (1.8V) Guard Ring Ground (1.8V) Stand-By SRAM Battery Backed Stand-By Power Supply (1.8V) Port Pins Power Supply (3.3V)
VAGND_ADC 188
VDD_GUARD 200
13
V 1.3, 2003-10
TC1920
Preliminary Table 1 Symbol VDD VSS
1)
Pin Definitions and Functions Pad1)
5) 6)
BGA In/ Functions 2) BALL Out Core Power Supply (1.8V) Ground for Core and Ports
The pin number describes the position of a signal on the silicon. The mapping of the pin number to the corresponding BGA ball is done according to the used package. The notification ',u' after the input/output type defines an internal pull-up resistor. An internal pull-down resistor is indicated by ',d'. For the lines AD[31:0] and A[23:0], the type of the pull device can be selected 's'. Output driver comparable to GPIO Medium Driver/Sharp Edge. The BGA balls for the 3.3V port power supply are: G11, G12, G7, G8, H12, H7, L12, L7, M11, M12, M7, M8. The BGA balls for the 1.8V core power supply are: A16, B16, B3, C4, D5, J4, L4, R4. The BGA balls for the digital ground are: A1, B2, C3, D4, D6, G10, G9, H10, H11, H8, H9, J10, J11, J12, J7, J8, J9, K10, K11, K12, K7, K8, K9, L10, L11, L8, L9, M10, M9.
2)
3) 4) 5)
6)
Data Sheet
14
V 1.3, 2003-10
TC1920
Preliminary System Architecture and Control 32-Bit TriCore CPU * * * * * * * * * * 32-bit architecture with 4-GByte unified data, program and input/output address space Fast automatic context-switch Dual 16 x 16 Multiply-accumulate (MAC) unit Saturating integer arithmetic Register based design with multiple variable register banks Bit handling Packed data operations Zero overhead loop Precise exceptions Flexible power management
Instruction Set with High Efficiency: * 16/32-bit instructions for reduced code size * Little endian byte ordering with support for big and little endian byte ordering at bus interface * Boolean, array of bits, character, signed and unsigned integer, integer with saturation, signed fraction, double word integers and IEEE-754 single precision floating-point data types * Bit, 8-bit byte, 16-bit half word, 32-bit word and 64-bit double word data formats * Powerful instruction set * Flexible and efficient addressing mode for high code density On-chip Code Memories PMU Scratch-Pad SRAM (CSRAM): The PMU memory consists of 24-KByte Code Scratchpad RAM (CSRAM) and 8-KByte Instruction Cache (ICACHE). Address range of the CSRAM: * D400 0000H - D400 5FFFH Boot ROM (BROM): The TC1920 contains 32 KByte of Boot ROM memory, which can be used for device operating mode initialization routines, bootstrap loader support or test functions. The address range of the Boot ROM is: * DFFF 8000H - DFFF FFFFH
Data Sheet
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TC1920
Preliminary On-chip Data Memories DMU Scratch-Pad SRAM (DSRAM): The DMU memory consists of 24-KByte Data Scratchpad RAM (DSRAM) and 8-KByte Data Cache (DCACHE). Address range of the DSRAM: * D000 0000H - D000 5FFFH Local Memory Bus Memory (LMBRAM): Address range of the 64 KByte Local Memory Bus Memory: * C000 0000H - C000 FFFFH (in segment 12 for cached operation) * E800 0000H - E800 FFFFH (in segment 14 for non-cached operation) FPI-Bus Data Memory (FPIDRAM): The FPI-Bus Data Memory (FPIDRAM) is a 16-KByte static RAM located on the FPIBus. It contains two parts: FPIDRAM0 and FPIDRAM1. One half of it (FPIDRAM1) can be used for standby power operation. Address range of the FPI Data Memory: * 9FFF 8000H - 9FFF BFFFH (in segment 9 for cached operation) * BFFF 8000H - BFFF BFFFH (in segment 11 for non-cached operation) On-chip PCP Memories PCP Code Memory (PCODE): The address range of the 16 KByte PCP Code Memory (PCODE) is: * F002 0000H - F002 3FFFH PCP Data Memory (PRAM): The address range of the 4 KByte PCP Data Memory (PRAM) is: * F001 0000H - F001 0FFFH
Data Sheet
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TC1920
Preliminary System Control Unit (SCU) The System Control Unit of the TC1920 basically handles all system control tasks. All these system functions are tightly coupled and therefore they are handled physically by one unit, the SCU. The system tasks of the SCU are: * * * * * * * * Clock Generation and Control Reset control Power Management control and wake-up Watchdog timer Trace port control Device identification Standby SRAM control External interrupt capability (8 sources)
System timer (STM) The System Timer is designed for global system timing applications requiring both high precision and long range. It is used by the CPU for software operating system issues. Features: * * * * * * Free-running 56-bit counter All 56 bits can be read synchronously Different 32-bit portions of the 56-bit counter can be read synchronously Driven by clock, f STM (normally identical with the system clock). Counting begins at power-on reset Continuous operation is not affected by any reset condition except power-on reset
Data Sheet
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TC1920
Preliminary External Bus Interface (EBU_LMB) EBU_LMB is connected to the Local Memory Bus (LMB) of the TC1920 and also to the FPI Bus. EBU_LMB is always a slave on the LMB and a master/slave on the FPI bus. Any LMB masters thus can access external memories or devices through EBU_LMB. Currently the maximum length of the bursts are according to the size of program and data cache lines, i.e. 8 x 32-bit words. Single transfers (non-burst) are supported for 8bit, 16-bit and 32-bit wide access.
E B U _L M B External Bus 32-bit L M B B us 64 -bit XBC B uffer S lo w e r D evices 50 M H z
SDRAM
DME F P I B us 32 -bit XM I
E xterna l M aster
E B U L 30 4 5 _L
E xte rn al B us U nit
Figure 4
EBU_LMB block diagram
Features supported in EBU_LMB: * * * * * * * * * * * * * * * * * * Local Memory Bus (LMB 64-bit) support. External bus frequency: LMB frequency = 1:1 or 1:2 or 1:4. Highly programmable access parameters. Intel-style and Motorola-style peripheral/device support. SDRAM support (burst access, multibanking, precharge, refresh). 16- and 32-bit SDRAM data bus and support of 64, 128 and 256MBit devices. Burst flash support. Multiplexed access (address & data on the same bus) when SDRAM is not present on the External Bus. Data Buffering: Code Prefetch Buffer, Read/Write Buffer. External master arbitration (compatible to C166 and other TriCore devices). 8 programmable address regions (1 dedicated for emulator). Little-endian and Big-endian support. CSGLB signal, dedicated pin, bit programmable to combine one or more CS lines, for buffer control. RMW signal reflecting a read-modify-write action. Signal for controlling data flow of slow-memory buffer. Slave unit for external (off-chip) master to access devices on the FPI bus. Master unit for FPI master to access external (off-chip) devices. Data Mover Engine.
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Data Sheet
TC1920
Preliminary Interrupt System * Flexible interrupt prioritizing scheme with 256 interrupt priority levels * Fast interrupt response * Service requests are serviced by the CPU or by the PCP (two independent interrupt buses, that can be selected by each interrupt source)
P C P In te rru p t A rb itra tio n B u s M o d u le A M o d u le K e rn e l n S e rvice R e q u e st Nodes
C P U In te rru p t A rb itra tio n B u s P C P In te rru p t C o n tro l PC P In te rru p t C o n tro l U n it (P IC U )
PCP K e rn e l 12
M o d u le B M o d u le K e rn e l n S e rvice R e q u e st Nodes
1 2 S e rvice R e q u e st Nodes
M a in In te rru p t C o n tro l CPU In te rru p t C o n tro l U n it (IC U )
M o d u le C M o d u le K e rn e l n S e rvice R e q u e st Nodes
CPU C o re 4
4 S e rvice R e q u e st Nodes
Figure 5
Block Diagram Interrupt System
Data Sheet
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TC1920
Preliminary Peripheral Control Processor (PCP)
C od e M e m ory PCODE P a ra m e te r M e m o ry PRAM
PCP P roc e s so r C o re
F P I-In te rfa c e
P C P S e rvice R eq . N o d e s PSRNs
P C P In te rrup t C o ntro l U n it P IC U
F P I B us
P C P In te rru p t A rbitra tio n B u s C P U In te rrup t A rbitratio n B u s
M C B 0 4 78 4 _ m o d
Figure 6
PCP block diagram
The PCP is designed to work in partnership with a host CPU and performs many of the tasks that would conventionally be performed by CPU interrupt service routines or a DMA controller. The PCP off-loads the host CPU from most of the time critical interrupts, easing the implementation of systems based on operating systems. In principle the PCP may be considered to be a conventional processor which only executes code in response to interrupt service requests (i.e. has no processing which is not at interrupt level). It has an architecture which efficiently supports DMA type of bus transactions to / from arbitrary devices and memory addresses and also some reasonable computational capabilities. Whenever the PCP responds to a PCP interrupt request (which has a specific interrupt priority level) it will use a register set ("context") specific to that individual interrupt level and will also generally execute code which is also specific to that interrupt level. For this reason the term "Channel" will be used throughout the remainder of this document to refer to all PCP resources associated with a particular PCP interrupt level. The architecture is flexible enough to allow the implementation of a subset of the commands/instructions as a simple DMA controller. The PCP has a Harvard architecture (i.e. separate code and data memory spaces). Any FPI bus master (including the PCP itself) can access both PCP code (PCODE) and data (PRAM) memory via the FPI bus.
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TC1920
Preliminary FPI Bus The Flexible Peripheral Interconnect Bus is designed with the requirements of highperformance Systems-on-Chip in mind. Key Features: * * * * * * * * * * Core independent Multi-master capability Demultiplexed operation Clock synchronous Peak transfer rate of up to 200 MBytes/s (@ 50 MHz bus clock) Address and data bus scalable (32 bit address bus, 32 bit data bus ) 8-/16- and 32 bit data transfers Broad range of transfer types from single to multiple data transfers Burst transfer capability EMI and power consumption minimized
LMB-Bus The Local Memory Bus is a synchronous, pipelined, split bus with variable block size transfer support. All signals relate to the positive clock edge. The protocol supports 8,16,32 & 64 bits single beat transactions and variable length 64 bits block transfers. Key Features: The LMB provides the following features: * * * * * * * Optimized for high speed and high performance 32 bit address, 64 bit data busses Central simple per cycle arbitration Slave controlled wait state insertion Address pipelining (max. depth - 2) Split transactions Variable block length - 2, 4 or 8 beats of 64 bit data
Data Sheet
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TC1920
Preliminary On-Chip Debug System (OCDS) The TC1920 architecture is supporting OCDS level 1 and 2. Level 1 2 Run Time Control Yes Yes System access via JTAG Yes Yes Trace bus No Yes No Yes Basic PC trace
Table 2 Module
Core-related and System Control Modules Address Range F7E0 FF00H F7E0 FFFFH I/O Lines AD[31:0], A[23:0], 27 control lines Interrupt Nodes CPU_SRC0..3 CPU_SRCSB PCP_SRC0..11 -
TriCore CPU Slave Registers (CPS)
Memory Management1) F7E1 8000H Unit (MMU) F7E1 80FFH Segment Protection Registers1) Core Debug1) (Core OCDS) TriCore CPU1) SFR, GPR F7E1 C000H F7E1 C0FFH F7E1 FD00H F7E1 FDFFH F7E1 FE00H F7E1 FFFFH
Program Memory Unit2) F87F FD00H (PMU) F87F FDFFH Data Memory Unit2) (DMU) Peripheral Control Processor (PCP) External Bus Unit (EBU) System Control Unit (SCU) F87F FC00H F87F FCFFH F000 3F00H F000 3FFFH F800 0000H F800 03FFH F000 0000H F000 00FFH
4 XTAL, PORST, EXI_SRC0..4 HRST, 8 EXIN, NMI, NMI3) 4 test, CLKOUT, BYPASS BCU_SRC
FPI Bus Control Unit (BCU)
F000 0200H F000 02FFH
Data Sheet
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TC1920
Preliminary Table 2 Module LMB Bus Control Unit (LCU) LMB to FPI Bus Bridge (LFI) Port Control (Ports 0, 1, 2, 3, 5) Debug Support (JTAG, OCDS) Core-related and System Control Modules (cont'd) Address Range F87F FE00H F87F FEFFH F87F FF00H F87F FFFFH F000 2800H F000 2CFFH F000 0400H F000 04FFH I/O Lines P0 (7), P1(7), P2(15), P3(15), P5(15) Interrupt Nodes LCU_SRC -
TRST, TCK, TDI, TDO, TMS, OCDSE, BRKIN, BRKOUT, 16 trace outputs
1) 2) 3)
This address range is also accessed via the CPS by the FPI bus. This address range is accessed via the LMB. The NMI is directly connected to the core (no SRC) and always acts on the highest priority. It is used as highest priority interrupt for the NMI input, the watchdog, the PLL and for wake-up via the RTC or via the EXIx inputs.
On-Chip Peripheral Units The TC1920 offers several on-chip peripheral units such as serial controllers, timer units, AD converter and Codec interface. Within the TC1920 all these peripheral units are connected to the TriCore CPU/system via the FPI (Flexible Peripheral Interconnect) Bus. Several IO lines on the TC1920 ports are reserved for these peripheral units to communicate with the external world. Peripheral Units of the TC1920: * Three Asynchronous/Synchronous Serial Channels with baudrate generator, parity, framing and overrun error detection, IrDA mode, FIFO buffers. * One High Speed Synchronous Serial Channels with programmable data length and shift direction * TwinCAN Module with two interconnected CAN nodes for high efficiency data handling via FIFO buffering and gateway data transfer * Serial Data Link Module compliant to SAE Class B J1850 specification * IIC module with connection to 2 external busses * 2 multi-functional General Purpose Timer Units with three 32-bit timer/counter * One Analog-to-Digital Converter Units with 8-bit, 10-bit, or 12-bit resolution and 6 analog inputs * Dual channel Codec interface * GPIO blocks
Data Sheet
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TC1920
Preliminary
Table 3 Module
Peripheral Modules Address Range F000 0A00H F000 0AFFH I/O Lines RDX0, TDX0 Interrupt Nodes ASC0_TSRC ASC0_RSRC ASC0_ESRC ASC0_TBSRC ASC1_TSRC ASC1_RSRC ASC1_ESRC ASC1_TBSRC ASC2_TSRC ASC2_RSRC ASC2_ESRC ASC2_TBSRC SSC_TSRC SSC_RSRC SSC_ESRC IIC_XP0SRC IIC_XP1SRC IIC_XP2SRC RTC_SRC GPTU0_SRC0..7 GPTU1_SRC0..7 CAN_SRC0..7 SDLM_SRC0..1
Asynchronous Serial Channel 0 (ASC0) Asynchronous Serial Channel 1 (ASC1) Asynchronous Serial Channel 2 (ASC2)
F000 0B00H F000 0BFFH
RDX1, TDX1
F000 0C00H F000 0CFFH
RDX2, TDX2
Synchronous Serial F000 0800H Channel (SSC) F000 08FFH Inter-IC Bus (IIC) F000 0500H F000 05FFH F000 0100H F000 01FFH F000 0300H F000 03FFH F000 0700H F000 07FFH F000 0600H F000 06FFH F010 0000H F010 0BFFH F000 2600H F000 26FFH
SCLK, MRST, MTSR SCL[1:0], SDA[1:0] GPTU0[7:0] GPTU1[7:0] RXDCAN[1:0], TXDCAN[1:0] RXJ1850, TXJ1850
Real Time Clock (RTC) System Timer Unit (STM) General Purpose Timer 0 (GPTU0) General Purpose Timer 1 (GPTU1) CAN (TwinCAN) SDLM (J1850)
Data Sheet
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TC1920
Preliminary Table 3 Module Speech Interface (Codec) Peripheral Modules (cont'd) Address Range F000 2400H F000 24FFH I/O Lines 2*2 analog IN, 2*2 analog OUT, CEXT, CODEC_DIS AIN[5:0] = P4, ADEMUX[2:0], ADEXTIN Interrupt Nodes CODEC_SRC0..5
Analog to Digital Converter (ADC)
F000 2200H F000 23FFH
ADC_SRC0..3
Asynchronous/Synchronous Serial Interfaces (ASC 0/1/2) The Asynchronous/Synchronous Serial Interface ASC provides serial communication between the TriCore and other microcontrollers, microprocessors or external peripherals. The implementation is held parametrizable in order to allow the usage of parallel busses of different width and with different protocols. Features: * Full duplex asynchronous operating modes - 8- or 9-bit data frames, LSB first - Parity bit generation/checking - One or two stop bits - Baudrate from 3.125 MBaud to 0.74 Baud (@ 50 MHz module clock) - Multiprocessor mode for automatic address/data byte detection - Loop-back capability * Half-duplex 8-bit synchronous operating mode - Baudrate from 6.25 MBaud to 637 Baud (@ 50 MHz module clock) * Double buffered transmitter/receiver * Interrupt generation - on a transmitter buffer empty condition - on a transmit last bit of a frame condition - on a receiver buffer full condition - on an error condition (frame, parity, overrun error) * Support for IrDA * Automatic Baudrate Detection * 8 Byte FIFO
Data Sheet
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TC1920
Preliminary
C lo c k C on tro l
f h w _c lk
A d d re s s D e c o de r T IR T B IR R IR E IR A B S T IR A B D E T IR
RXD ASC M o du le (K e rn e l) TXD P ort C o ntro l
RXD TX D
Interru p t C on tro l
M C A 0 5 2 53
Figure 7
ASC Interface Diagram
Data Sheet
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TC1920
Preliminary High-Speed Synchronous Serial Interface (SSC) The High Speed Synchronous Serial Interface SSC provides serial communication between microcontrollers, microprocessors or external peripherals. The SSC supports full-duplex and half-duplex synchronous communication up to 25 MBaud (@ 50 MHz module clock). The serial clock signal can be generated by the SSC itself (master mode) or be received from an external master (slave mode). Data width, shift direction, clock polarity and phase are programmable. This allows communication with SPI-compatible devices. Transmission and reception of data are double-buffered. A 16-bit baud rate generator provides the SSC with a separate serial clock signal. Features: * Master and slave mode operation - Full-duplex or half-duplex operation * Flexible data format - Programmable number of data bits : 2 to 16 bit - Programmable shift direction : LSB or MSB shift first - Programmable clock polarity : idle low or high state for the shift clock - Programmable clock/data phase : data shift with leading or trailing edge of SCLK * Maximum baudrates: 25 MBaud in Master, 12.5 in Slave mode (@ 50 MHz module clock) Interrupt generation - on a transmitter empty condition - on a receiver full condition - on an error condition (receive, phase, baudrate, transmit error) * Three pin interface
C lo c k C on tro l
f h w _c lk
Slave Master RXD TXD RXD TXD S la v e M a s te r SCLK P o rt C o n tro l M TSR
A d d re s s D e c o de r E IR Interru p t C on tro l R IR T IR
SSC M o d ule (K erne l)
M RST
SCLK
M C B 04 5 0 5_ m o d
Figure 8
SSC Interface Diagram
Data Sheet
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TC1920
Preliminary Inter-IC Interface (IIC) IIC supports a certain protocol to allow devices to communicate directly with each other via two wires. One line is responsible for clock transfer and synchronization (SCL), the other is responsible for the data transfer (SDA). The on-chip IIC Bus module connects the platform buses to other external controllers and/or peripherals via the two-line serial IIC interface. The IIC Bus module provides communication at data rates of up to 400 kBit/s and features 7-bit addressing as well as 10-bit addressing. This module is fully compatible to the IIC bus protocol.
G e ne ric da ta line IIC K e rn el G e ne ric clock lin e IIC M o du le
SDA0 SDA1 SCL0 SCL1
Figure 9
IIC Bus Line Connections
The module can operate in three different modes: Master mode, where the IIC controls the bus transactions and provides the clock signal. Slave mode, where an external master controls the bus and provides the clock signal. Multimaster mode, where several masters can be connected to the bus, i.e. the IIC can be master or slave. The module unloads the CPU of low level tasks like: * * * * * * * * * * * (De)Serialization of bus data. Generation of start and stop conditions. Monitoring the bus lines in slave mode. Evaluation of the device address in slave mode. Bus access arbitration in multimaster mode. Extended buffer allows up to 4 send/receive data bytes to be stored. Selectable baud rate generation. Support of standard 100 kBaud and extended 400 kBaud data rates. Operation in 7-bit addressing mode or 10-bit addressing mode. Flexible control via interrupt service routines or by polling. Dynamic access to up to 2 physical IIC busses.
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IIC Features:
Data Sheet
TC1920
Preliminary CAN Interface (TwinCAN) Figure 10 shows a global view of the functional blocks of the TwinCAN module.
T w in C A N M o d ule K e rn e l C lo c k C on tro l
fC A N
CAN Node A
CAN N od e B TXDCA
A d d re s s D e c o de r
RXDCA M es s a ge O bje ct B uffe r P o rt C o n trol TXDCB RXDCB T w inC A N C on tro l
M C B 0 4 51 5
Interru p t C on tro l
Figure 10
General Block Diagram of the TwinCAN Interfaces
TwinCAN Features: * * * * CAN functionality according to CAN specification V2.0 B active. Dedicated control registers are provided for each CAN node. A data transfer rate up to 1MBaud is supported. Flexible and powerful message transfer control and error handling capabilities are implemented. * Full-CAN functionality: 32 message objects can be individually - assigned to one of the two CAN nodes, - configured as transmit or receive object, - participate in a 2,4,8,16 or 32 message buffer with FIFO algorithm, - setup to handle frames with 11 bit or 29 bit identifiers, - provided with programmable acceptance mask register for filtering, - monitored via a frame counter, - configured to Remote Monitoring Mode. * Up to eight individually programmable interrupt nodes can be used. * CAN Analyzer Mode for bus monitoring is implemented. The TwinCAN module has four IO lines. The TwinCAN module is further supplied by a clock control, interrupt control, address decoding, and port control logic.
Data Sheet
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TC1920
Preliminary The CAN module contains two Full-CAN nodes operating independently or exchanging data and remote frames via a gateway function. Transmission and reception of CAN frames is handled in accordance to CAN specification V2.0 part B (active). Each of the two Full-CAN nodes can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. Both CAN nodes share the TwinCAN module's resources in order to optimize the CAN bus traffic handling and to minimize the CPU load. The flexible combination of Fullfunctionality and FIFO architecture reduces the efforts to fulfill the real-time requirements of complex embedded control applications. Improved CAN bus monitoring functionality as well as the increased number of message objects permit precise and comfortable CAN bus traffic handling. Depending on the application, each of the 32 message objects can be individually assigned to one of the two CAN nodes. Gateway functionality allows automatic data exchange between two separate CAN bus systems, which reduces CPU load and improves the real time behavior of the entire system. The bit timings for both CAN nodes are derived from the peripheral clock (fCAN) and are programmable up to a data rate of 1 MBaud. A pair of receive and transmit pins connect each CAN node to a bus transceiver.
Data Sheet
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TC1920
Preliminary Serial Data Link Module (J1850) Figure 11 shows a global view of the functional blocks of the J1850 interface.
f S D LM
C lo c k C on tro l
RXD A d d re s s D e c o de r SDLM M o d u le (K e rn e l) TXD P ort C on tro l
R X J 1 85 0 T X J 1 8 50
Interru p t C on tro l
M C B 0 4 5 50
Figure 11
General Block Diagram of the SDLM Interface
The J1850 module communicates with the external world via two I/O lines, the J1850 bus. The RXD line is the receive data input signal and TXD is the transmit data output signal. The Serial Data Link Module provides serial communication to a J1850 based serial bus. J1850 bus transceivers have to be implemented externally in a system. The J1850 module is conform to the SAE Class B J1850 specification and compatible to class 2 protocol. General SDLM Features: * * * * * * * * * * * * * * * Compliant to SAE Class B J1850 specification Full support of GM class 2 protocol Variable Pulse Width (VPW) format with 10.4 kBaud High speed receive/transmit 4x mode with 41.6 kBaud Digital noise filter Power save mode and automatic wake up upon bus activity Support of single byte headers or consolidated headers CRC generation & check Support of block mode for receive and transmit 11 bytes transmit buffer Double buffered 11 bytes receive buffer Support of In-frame response (IFR) types 1,2,3 Advanced interrupt handling for RX, TX and error conditions All interrupt sources can be enabled/disabled individually Support of automatic IFR for types 1,2 for three byte consolidated headers
Data Link Operation Features:
Data Sheet
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TC1920
Preliminary Timer Units (GPTU 0/1) Figure 12 shows a global view of all functional blocks of one GPTU module.
IN 0 IN 1 IN 2 IN 3 IN 4 IN 5 IN 6 IN 7 O UT0 O UT1 O UT2 O UT3 O UT4 O UT5 O UT6 O UT7 P ort C o n tro l IO 0 IO 1 IO 2 IO 3 IO 4 IO 5 IO 6 IO 7
C lo c k C on tro l
fGPTU
P 0 .0 / G P T 0 P 0 .1 / G P T 1 P 0 .2 / G P T 2 P 0 .3 / G P T 3 P 0 .4 / G P T 4 P 0 .5 / G P T 5 P 0 .6 / G P T 6 P 0 .7 / G P T 7
M C B 0 5 0 52 _ m o d ifie d
A d d re s s D e c o de r SR0 SR1 SR2 SR3 SR4 SR5 SR6 SR7 G PTU M o d ule (K e rne l)
Interru p t C on tro l
Figure 12
General Block Diagram of the GPTU Interface
The GPTU consists of three 32-bit timers designed to solve such application tasks as event timing, event counting, and event recording. The GPTU communicates with the external world via eight inputs and eight outputs. The three timers of the GPTU module T0, T1, and T2, can operate independently from each other, or can be combined: General Features: * * * * All timers are 32-bit precision timers with a maximum input frequency of fGPTU/2. Events generated in T0 or T1 can be used to trigger actions in T2 Timer overflow or underflow in T2 can be used to clock either T0 or T1 T0 and T1 can be concatenated to form one 64-bit timer
Features of T0 and T1: * Each timer has a dedicated 32-bit reload register with automatic reload on overflow * Timers can be split into individual 8-, 16-, or 24-bit timers with individual reload registers * Overflow signals can be selected to generate service requests, pin output signals, and T2 trigger events * Two input pins can determine a count option
Data Sheet
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TC1920
Preliminary Features of T2: * Optionally count up or down * Operating modes: - Timer - Counter - Incremental Interface Mode * Options: - External start/stop, one-shot operation, timer clear on external event - Count direction control through software or an external event - Two 32-bit reload/capture registers * Reload modes: - Reload on overflow or underflow - Reload on external event: positive transition, negative transition, or both transitions * Capture modes: - Capture on external event: positive transition, negative transition, or both transitions - Capture and clear timer on external event: positive transition, negative transition, or both transitions * Can be split into two 16-bit counter/timers * Timer count, reload, capture, and trigger functions can be assigned to input pins. T0 and T1 overflow events can also be assigned to these functions. * Overflow and underflow signals can be used to trigger T0 and/or T1 and to toggle output pins * T2 events are freely assignable to the service request nodes.
Data Sheet
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TC1920
Preliminary Analog to Digital Converter (ADC) Figure 13 shows a global view of the ADC module kernel with the module specific interface connections.
V SSA V DD M V DD A V SSM V AR EF
V AGND
C lo c k C on tro l
fA D C
P o rt C o n trol
EM UX0 EM UX1 EM UX2
A d d re s s D e c o de r SR0 SR1 SR2 SR3
A IN 0 A IN 1
Interru p t C on tro l
ADC M o du le K e rn e l ASGT ETR, EG T In te rrup t Q T R , Q G T In p uts TTR, TG T
A IN 5 E X I0IN E X I7IN A D E X T IN
T C 1 92 0 _ A D C _ blo ck dia g ram
SW 0TR=0
S W 0G T= 1
Figure 13
General Block Diagram of the ADC module
The on-chip ADC module of the TC1920 is an analog to digital converter with 8-bit, 10bit or 12-bit resolution including sample & hold functionality. The A/D converter operates by the method of the successive approximation. A multiplexer selects between up to 6 analog input channels. Conversion requests are generated either under software control or by hardware. An automatic self-calibration adjusts the ADC module to changing temperatures or process variations.
Data Sheet
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TC1920
Preliminary Features: The following functionality has been implemented in the on chip ADC module to fulfill the enhanced requirements of embedded control applications: * * * * * * * * * * * * * * * 8-bit, 10-bit, 12-bit A/D Conversion Successive approximation conversion method Total Unadjusted Error (TUE) of 2 LSB @ 10-bit resolution Integrated sample and hold functionality 6 analog input channels Dedicated control and status registers for each analog channel Flexible conversion request mechanisms Selectable reference voltages for each channel Programmable sample and conversion timing schemes Limit checking Flexible ADC module service request control unit Automatic control of external analog multiplexer Equidistant samples initiated by timer External trigger inputs for conversion requests Power reduction and clock control feature
Real Time Clock Unit RTC The Real Time Clock (RTC) module is basically an independent timer chain and counts clock ticks. The base frequency of the RTC can be programmed via a reload counter. The RTC can work fully asynchronous to the system frequency and is optimized on low power consumption. Features: The RTC serves different purposes: * * * * Absolute system clock to determine the current time and date Cyclic time based interrupt Alarm interrupt for wake up on a defined time 48-bit timer for long term measurements
Data Sheet
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TC1920
Preliminary Codec Interface The speech A/D and D/A converters (called codec) is designed for telephone and speech recognition quality. They can be used for microphone / earpiece applications. The TC1920 configuration implements a dual channel speech codec connected to the FPI bus.
VDD
C O D0
VSS
COD0
V DD V SS
CO D 1 CO D 1
ch0 n on -inv. inpu t C lock C on trol
f pe r
A I0 + A I0 A O 0+ A O 0A I1 + A I1 A O 1+ A O 1C O D E C _ D IS CEXT M UTE0 M UTE1 IIS sig na ls
ch0 in v. inp ut ch0 n on -inv. outp ut ch0 in v. ou tp ut
A d dre ss D e co de r SR0 SR1 SR2 SR3 SR4 SR5 CO DEC M o dule K e rn el
ch1 n on -inv. inpu t ch1 in v. inp ut ch1 n on -inv. outp ut ch1 in v. ou tp ut clock disab le external clock inp ut m ute ch ann el 0 m ute ch ann el 1
In terrup t C on trol
V RE F
COD
VGND
COD
5
C od ec b ypass
Figure 14
General Codec Overview
General Purpose I/Os (GPIO) * * * * Push/pull output drivers 3.3 Volt operation for GPIO Programmable pull-up/-down devices at all pins Optional Open Drain Output Mode
Data Sheet
36
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TC1920
Preliminary Power Supply Figure 15 shows the TC1920 power supply concept, where certain logic modules are individually supplied with power. In this way, the noise margin is improved in the especially sensitive modules, like the A/D converter and the CODEC.
V D DA V SSA V D DA V SS A V DD A V SSA V DD A V SSA V D DA V SS A V DD A V SSA
M A IN OSC
RTC OSC
PLL (ana log)
ADC (ana log)
CO DEC 0 (a na lo g)
CODEC 1 (ana log)
V D DP V SS P X V D DP V SS P Y V D D_SB V D DR V SS V DD V SS VDD V SS B atte ry B acked S ta nd- B y S RAM A LL D IG IT A L C O R E CO MPO NENTS
Figure 15
TC1920 Power Supply Concept
Data Sheet
37
V 1.3, 2003-10
TC1920
Preliminary Power-Up Sequence During Power-Up reset pin PORST has to be held active until both power supply voltages have reached at least their minimum values. During the Power-Up time (rising of the supply voltages from 0 to their regular operating values) it has to be ensured, that the core VDD power supply reaches its operating value first, and then the GPIO VDDP power supply. During the rising time of the core voltage it must be ensured that 0< VDD-VDDP <0.5 V. During power-down, the core and GPIO power supplies VDD and VDDP respectively, have to be switched off until all capacitances are discharged to zero, before the next power-up.
Note: The states of the pins are undefined when only the port voltage VDDP is on.
Data Sheet
38
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TC1920
Preliminary ID Register Table Table 4 SCU_ID MANID CHIPID RTID RTC_ID BCU_ID STM_ID JDP_ID IIC_ID GPTU0_ID GPTU1_ID SSC_ID ASC0_ID ASC1_ID ASC2_ID ADC_ID CODEC_ID SDLM_ID PCP_ID CAN_ID CPS_ID MMU_ID CPU_ID EBU_ID DMU_ID PMU_ID LCU_ID LFI_ID
Data Sheet
List of TC1920 ID registers Address F000 0008H F000 0070H F000 0074H F000 0108H F000 0208H F000 0308H F000 0408H F000 0508H F000 0708H F000 0608H F000 0808H F000 0A08H F000 0B08H F000 0C08H F000 2208H F000 2408H F000 2608H F000 3F08H F010 0008H F7E0 FE08H F7E1 8008H F7E1 FE18H F800 0008H F87F FC08H F87F FD08H F87F FE08H F87F FF08H
39
Short Name Description SCU Identification Register Manufacturer Identification Register Chip Identification Register RTC Module Identification Register BCU Identification Register System Timer Module Identification Register JTAG/OCDS Module Identification Register IIC Module Identification Register GPTU Module Identification Register GPTU Module Identification Register SSC Module Identification Register ASC Module Identification Register ASC Module Identification Register ASC Module Identification Register ADC Module Identification Register Codec Identification Register SDLM Module Identification Register PCP Module Identification Register CAN Module Identification Register CPU Module Identification Register MMU Identification Register CPU Identification Register EBU_LMB Identification Register DMU Identification Register PMU Module Identification Register LCU Identification Register LFI Identification Register
Value 0019 C002H 0000 1820H 0000 8902H 0000 0000H 0000 5A04H 0000 6A06H 0000 C002H 0000 6305H 0000 4604H 0001 C002H 0001 C002H 0000 4503H 0000 44E1H 0000 44E1H 0000 44E1H 0000 3104H 001C C002H 0000 4204H 0020 C003H 0000 4110H 0015 C004H 0009 C002H 000A C003H 0014 C003H 0008 C002H 000B C002H 000F C003H 000C C003H
V 1.3, 2003-10
Redesign Tracing Identification Register F000 0078H
TC1920
Preliminary Electrical characteristics
Parameter Interpretation The parameters listed in the following partly represent the characteristics of the TC1920 and partly its demands on the system. To aid in interpreting the parameters right, when evaluating them for a design, they are marked in column "Symbol": CC (Controller Characteristics): The logic of the TC1920 will provide signals with the respective characteristics. SR (System Requirement): The external system must provide signals with the respective characteristics to the TC1920.
Data Sheet
40
V 1.3, 2003-10
TC1920
Preliminary Absolute Maximum Ratings Parameter Ambient temperature Symbol -40 -65 - -0.5 -0.3 -0.3 -0.3 -0.5 -10 - - Limit Values min. max. 85 150 125 4.2 2.1 2.1 2.1 4.2 10 |100| 1.4 C C C V V V V V mA mA W PLL under bias under bias Unit Notes
TA TST Storage temperature Junction temperature TJ Voltage on I/O Supply pins with VDDP
respect to ground (VSS) Voltage on Core Supply pins with respect to ground (VSS) Voltage on PLL Supply pins with respect to ground (VSS)
VDD VDDPLL
Voltage between Oscillator VDDOSC Supply Pins and ground (VSS). Voltage on any pin with respect VIN to ground (VSS) Input current on any pin during IOV overload condition Absolute sum of all input currents at overload condition Power dissipation IOV
PDISS
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN>VDD or VINData Sheet
41
V 1.3, 2003-10
TC1920
Preliminary Package Parameters (P-LBGA-260) Parameter Power dissipation Thermal resistance Operating Conditions The following operating conditions must not be exceeded in order to ensure correct operation of the TC1920. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed. Parameter Supply voltage Symbol Limit Values min. max. 3.61) 1.892) 1.89 1.89 0 -5 5 V V V V V mA I/O supply Core supply PLL supply Oscillator supply 3.0 1.71 1.71 1.71 Unit Notes Symbol Limit Values min. max. 1.4 27.8 W - K/W Chip to ambient - - Unit Notes
PDISS RTHA
Ground voltage Input current on any pin during overload condition
VDDP VDD VDDPLL VDDOSC VSS
IOV
VOV > VDDP + 0.3V VOV < VSS - 0.3V
Absolute sum of all input | IOV| currents at overload condition Ambient temperature under bias CPU clock External Load Capacitance
1)
-
|50|
mA
TA fCPU CL
-40 - -
85 100 50
C MHz pF
Voltage overshoot to 4 V is permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h Voltage overshoot to 2 V is permissible, provided the pulse duration is less than 100 s and the cumulated summary of the pulses does not exceed 1 h
2)
Data Sheet
42
V 1.3, 2003-10
TC1920
Preliminary DC Characteristics GPIO pins Parameter Output low voltage (strong driver) Output high voltage (strong driver) Output low voltage (medium driver)1) Output high voltage (medium driver)1) Output low voltage (weak driver)1) Output high voltage (weak driver)1) Input low voltage Input high voltage Symbol VOL VOH VOL VOH VOL VOH VIL VIH Limit values min. 2.4 2.4 2.4 -0.3 2.0 max. 1 0.4 0.4 0.4 0.8 V V V V V V V Unit Test Conditions IOL = 10 mA IOL = 2.5 mA IOH = - 2.5 mA IOL = 1 mA IOH = - 1 mA IOL = 100 A IOH = - 100 A LVTTL whatever is lower 0V< Vin < VDDP VOUT = 2.0V VOUT = 0.8V VOUT = 0.8V VOUT = 2.0V f = 1MHz @ TA = 25oC
VDDP+0.3 V or 3.7V 500 1 0.8 10 nA A A A A pF
Input leakage current Pull-up current 2) Pull-up current
3)
IOZ1 |IPUH | |IPUL| |IPDL| |IPDH| CIO
20 20 -
Pull-down current Pull-down current Pin capacitance1)
1) 2) 3)
Not subject to production test, verified by design/characterization. The maximum current that may be drawn while the respective signal line remains inactive. The minimum current that must be drawn in order to drive the respective signal line active.
Data Sheet
43
V 1.3, 2003-10
TC1920
Preliminary NMI Pin NMI Pin is an input pin with different Pull-Up characteristics than other pins. The related characteristics are given in the following table Parameter Symbol Limit values min. Max. current allowed |IPUH | through the Pull-Up device while pin (input) voltage remains still at the high level Min. current needed |IPUL | through the Pull-Up device so that pin voltage is driven to the low level. max. 4 uA Unit Test Conditions VOUT=2.0V
100
-
uA
VOUT=0.8V
Note: NMI Pin does not have a Pull-Down device.
Oscillator Pins
Parameter Input leakage current (analog input) at XTAL11) Input low voltage XTAL1 Input high voltage XTAL12)
Symbol IOZ1 CC VILX SR VIHX SR
Limit values min. max. 200
Unit nA
Test Conditions 0V< Vin < VDDP
0.8
0.3 VDD-0.3 VDD-0.35 VDD-0.4 VDD-0.43 20 0.5
V V
fOSC=4MHz fOSC=8MHz fOSC=12MHz fOSC=16MHz 0V < VIN < VDD 0V < VIN < VDD
XTAL1 input current XTAL3 input current2)
1) 2)
IIX1 CC IIX3 CC
-
A A
Only applicable in deep sleep mode Not subject to production test, verified by design/characterization.
Data Sheet
44
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TC1920
Preliminary IIC Pins Each IIC Pin is an open drain output pin with different characteristics than other pins. The related characteristics are given in the following table Parameter Output low voltage Input high voltage1) Input low voltage1) Input leakage current Pin capacitance1)
1)
Symbol VOL CC VIH SR VIL SR IOZ2 CC CIO CC
Limit values min. 0.7VDDP -0.3 max. 0.4 0.6 3.6 0.3VDDP + - 500 10
Unit V V V nA pF
Test Conditions 3 mA 6 mA -
f=1MHz@ TA=25oC
Not subject to production test, verified by design/characterization.
Note: No 5 V IIC interface is supported with these pads. Only voltages lower than 3.60 V must be applied to these pads. Note: IIC pins have no Pull-Up and Pull-Down devices.
Data Sheet
45
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TC1920
Preliminary ADC Analog I/O DC Characteristics
Parameter Core supply voltage Analog supply voltage Analog supply ground Reference voltage3) Reference ground Analog input voltage Internal A/D Converter clock Input leakage current (analog input) Input leakage current ( VAGnd , VARef) Overload current
Symbol VDD SR VDDA SR VSSA SR VAREF VAGND VA fANA IOZ1 CC IOZ2 CC IAOV SR
Limit values min. 1.71 3.0 -0.1 1.5 VSSA - 0.05 0.5 -2 typ. 1.8 3.3 0.0 max. 1.89 3.6 +0.1 VDDA+ 0.05
Unit Test Conditions V V V V V V -
VSSA VSSA + 0.05 VAREF 3.5 200 500 +5 1.0x10-4 1.5x10-3 -
VAGND -
MHz nA nA mA 0V< Vin < VDDA 0V< Vin < VDDA
1) 5)
Overload coupling factor2) kA Sample time Conversion time3) tBC=1/fBC, tDIV=1/fDIV, see Figure 17. ts tc
IAOV>0 3) IAOV<0 for channel n for 8- bit conversion for 10- bit conversion for 12- bit conversion
CC 4*(CHCONn.STC+2)*tBC CC tS + 40*tBC + 2*tDIV tS + 48*tBC + 2*tDIV tS + 56*tBC + 2*tDIV
Data Sheet
46
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TC1920
Preliminary Parameter Total unadjusted error4) Symbol TUE CC Limit values min. typ. max. 1 LSB 2 LSB 6 LSB5) On resistance of the transmission gates in the analog voltage path7) Resistance of the reference voltage path7) RAIN CC RREF CC 1900 Ohm Unit Test Conditions for 8- bit conversion for 10- bit conversion for 12- bit conversion
2000 10 15 15 -
Ohm pF pF pF
Switched capacitance at CAINSW the analog voltage input.7) CC Total capacitance at analog voltage input 6) Switched capacitance at the positive reference voltage input.7)
1)
CAINTOT CC CAREFSW CC
Analog overload conditions during operation occur if the voltage on the respective ADC pin exceeds the specified operating range (i.e. VAOV > VDDP+0.3V or VAOV < VSSP -0.3V ) or a short circuit condition occurs on the respective ADC pin. The absolute sum of input leakage and IAOV currents on all port pins must not exceed 10 mA at any time. The supply voltage (VDD, VDDP and VSS, VSSP ) must remain within the specified limits. Under short-circuit conditions the corresponding pin is not ready for use. The overload coupling factor (kA) defines the worst case relation of an overload condition (IOV) at one pin to the resulting total leakage current (IleakTOT) into an adjacent pin: |IleakTOT| = kA x |IOV| + IOZ1V Thus under overload conditions an additional error leakage voltage (VAEL) will be induced onto an adjacent analog input pin due to the resistance of the analog input source (RAIN). That means VAEL = RAIN x |IleakTOT|. Please see also the analog/digital converter specification, chapter "Error Through Overload Conditions", for further explanations. The nominal conversion time is valid for VAREF>3.0. For VAREF<3.0, it is approximately double. At VAREF=+3.3V and VAGND in the specified range. For VAREF<3.3V, TUE rise and is to be multiplied with a factor of 3.3/Vref. For VAGND outside the specified range, TUE is not guaranteed. Tested in production on request. Standard production test is 10-bit TUE test. Not subject to production test, verified by design/characterization. Simulation values.
2)
3) 4)
5) 6) 7)
Data Sheet
47
V 1.3, 2003-10
TC1920
Preliminary
R A IN , S o urce
R A IN , O n
A /D C on v e rte r
V A IN
=
C A IN , B lo ck
C A IN T O T - C A IN S W
C A IN S W
M C S 0 4 87 9
Figure 16
Equivalent Circuitry of an Analog Input
A/D C onverter M odule
fA D C
P e rip he ral C loc k D iv id e r (1:1 ) to (1 :8 )
f D IV
P ro g ra m m a b le C lo ck D iv id e r (1 :1 ) to (1 :2 5 6)
fBC
1 :4
f A N A P rog ra m m a b le
C o un te r
S am ple T im e t S
C O N .P C D A rbite r (1:20 )
C O N .C T C
C H C O N n.S T C C o n tro l/S tatu s L og ic In te rru pt L o g ic E xte rn a l T rig ge r L og ic E x te rn a l M ultip lex e r Lo g ic R eq u e st G e n e ra tio n L o g ic
f T IM E R
C o n trol U nit (T im e r)
M C A 0 4 6 57 _ m o d
Figure 17
ADC Clock Circuit
Data Sheet
48
V 1.3, 2003-10
TC1920
Preliminary Codec Electrical Characteristics
Parameter Digital supply voltage Analog supply voltage Analog supply ground Analog reference ground Analog input voltage (RMS) Analog output voltage (RMS) Input Resistace of the Analog Inputs4)
Symbol VDD VDDA VSSA VAGND VAIN VAOUT Ra
Limit values min. 1.71 3.0 -0.1 1.14 typ. 1.8 3.3 0.0 1.2 max. 1.89 3.6 +0.1 VSSA+ 0.05 0.775 0.775 30 -
Unit V V V V Vrms Vrms
Test Conditions
External reference voltage VAREF1)
+1.262) V
VSSA- VSSA 0.05
3)
kOhm differential input, gain: -12,-6, 0 dB kOhm single-ended input, gain: -12,-6, 0 dB kOhm differential input, gain: 6 to 30 dB kOhm single-ended input, gain: 6 to 30 dB V AGCCR. BGPSEL[1,0] =00
-
15
-
-
60
-
-
30
-
Internal Reference Voltage Vref (Bandgap Voltage)5)
1)
VBGP
1.1
1.2
1.3
Reference voltage outside the nominal range causes reduced dynamic range, decreased distortion/clipping margins, increased/decreased gain. VSSA=VAGND=0V Please take the gain settings of the analog preamplifier into account, therefore Vimaxreal=Vimax/gain Simulation value. For external usage only, Bandgap reference voltage is strongly dependent on the external load (<500 MOhm). In this case, high impedance buffer must be used.
2) 3) 4) 5)
Data Sheet
49
V 1.3, 2003-10
TC1920
Preliminary Codec ADC and DAC path characteristics
Parameters Attenuation distortion (ref. freq. 1014 Hz) (ref. level 0dBm0)2)
min.
typ.
max.
Unit dB dB dB dB dB
Test conditions1)
0 -0.25 -0.25 -0.25 0 -55 -0.3 -0.6 -1.6 -80 -80 -60 -0.8 0
0.25 0.45
< 0.025 0.025-0.0375 0.0375-0.3 0.3-0.425 > 0.425 at 0dBm0 +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 receive &transmit
Signal to total distortion Gain tracking (ref. freq. 1014 Hz) (ref. level 0dBm0)2) Idle channel noise
-45 0.3 0.6 1.6 -75 -75 -50 0.8
dB dB dB dB dBm 0 dB dB dB
Cross talk Harmonic distortion Gain (ref. freq. 1014 Hz) (ref. level 0dBm0)2) Power supply rejection ratio (PSRR)
1)
at 0dBm0 receive &transmit
-
-60 -40
-35 -35
dB dB
Receive (0.0375-0.425)3) Transmit (0.0375-0.425)3)
Values given in this table are valid for all sampling frequencies.
2)
3)
0dBm0 is equivalent to -12dBm is equal to 194.7 mVRMS.
Supply ripple 70 mV.
Note: Numbers without units in the test conditions column are relative frequency values to the chosen sampling frequency. e.g. 0.425 equals 3.4 kHz @ 8 kHz sampling frequency.
Data Sheet
50
V 1.3, 2003-10
TC1920
Preliminary Power Supply Current
Parameter Active mode supply current2) 3) Deep sleep mode supply current
1)
Symbol
Limit values typ.
1)
Unit mA mA mA
Test Conditions Sum of all IDD. at 1.8V Core Supply at 1.8V Core Supply
max. - - -
IDD
260 170 0.25
Idle mode supply current4) IID
IDDS
Typical values are measured at 25C, CPU clock at 100MHz and nominal supply voltage, i.e. 3.3V for VDDP and 1.8V for VDD, VDDPLL, VDDOSC
2) 3)
PORST=VIH
The typical power consumption values in active mode are measured while running a typical application pattern. The power consumption of modules can increase or decrease using different application programs. The PLL is bypassed and powered down during this measurement. CPU is in idle state, input clock to all peripherals are enabled.
4)
AC Characteristics Operating Conditions apply. Output Rise/Fall Times GPIO pins Rise/fall time measurements are made between 10% and 90%. The following table is valid for the GPIO pins pad drivers. Output pad characteristics are controllable via DRVCTRx registers.
Pad Modus rise / fall time Strong driver * sharp edge * medium edge1) * soft edge1)
1)
Symbol
Limit values min. max. 3 6 12
Temp Unit Comp yes yes yes ns ns ns
Test Conditions @50pF @50pF @50pF
SF SM SS
-
Not subject to production test, verified by design/characterization.
Data Sheet
51
V 1.3, 2003-10
TC1920
Preliminary Timing Characteristics (Operating Conditions apply)
Note: Timing parameters are not subject to production test, they are verified by design/ characterization.
2 .4 V
2 .0 V
T e st P oin ts
2 .0 V 0 .8 V
M C T 0 4 88 0
0 .4 V
0 .8 V
AC inputs during testing are driven at 2.4V for a logic "1" and 0.4V for a logic "0". Timing measurements are made at VIHmin for a logic "1" and VILmax for a logic "0". Figure 18 Input/Output Waveforms for AC Tests - for GPIO, Dedicated and EBU pins
External Oscillator at XTAL1 Timing Requirements (Operating Conditions apply) Parameter Main Oscillator XTAL frequency1) Frequency of an external oscillator driving at XTAL12) Input Clock high time Input Clock low time Input Clock rise time Input Clock fall time
Data Sheet 52
Symbol with/without PLL with PLL3) without PLL4)
Limits min. max. 16 25 25 - - 7 7 4 4 -
Unit MHz MHz ns ns ns ns
fOSC SR fOSCDD
SR
t1 t2 t3 t4
SR 16 SR 16 SR - SR -
V 1.3, 2003-10
TC1920
Preliminary
1) 2)
Oscillator Bypass Pin P3.11 latch-in value high. Internal oscillator provides the input clock signal. Oscillator Bypass Pin P3.11 latch-in value low. Internal oscillator disabled. External oscillator provides the input clock signal. Internal PLL provides the system clock. BYPASS pin latch-in value low. PLL prescaler value P=1. Internal PLL bypassed. BYPASS pin latch-in value high. External oscillator provides the system clock directly. When ADC and CODEC modules are active their frequency limitations must be taken into consideration, together with LMB/FPI bus frequency ratio. Otherwise, minimum frequency in this mode can go as low as zero.
3) 4)
tO SC
In p u t C lo c k at XTAL1 0 .5 V D D O S C
t1
t2
t4
t3
V IH X V IL X
M C T 04 8 8 2
Figure 19
External Clock at XTAL1 Requirements
Note: VDDOSC, VIHX and VIHL are defined in the Oscillator Pins DC Characteristics Chapter. Note: It is strongly recommended to measure the oscillation allowance (negative resistance) in the final target system (layout) to determine the optimal parameters for the oscillator operation. Please refer to the limits specified by the crystal supplier.
Data Sheet
53
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TC1920
Preliminary CPU Clock Timing (Operating Conditions apply; CL = 50 pF) Parameter CLKOUT period CLKOUT high time CLKOUT low time CLKOUT rise time CLKOUT fall time Symbol Limits min. max. - - - 3 3 ns ns ns ns ns Unit
tCLKOUT 10
CC
t1 t2 t3 t4
CC CC CC CC
4 4 - -
t C P U C LK
C LK OU T 0 .5 V D D
t1
t2
t4
t3
0 .9 V D D 0 .1 V D D
M C T 0 4 88 3
Figure 20
CLKOUT Timing
Data Sheet
54
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TC1920
Preliminary PLL Parameters Parameter Accumulated jitter VCO frequency range Symbol Limit Values1) min. max. - MHz MHz MHz MHz MHz MHz MHz MHz s 1502) 200
3)
Unit
DN fVCO
see Figure 21 100 150 200 250
2504) 3005) 802) 1303) 1804) 2305) 200
PLL base frequency
fPLLBASE
20 20 20 20
PLL lock-in time
1) 2) 3) 4) 5)
tL
-
Not subject to production test, verified by design/characterization. @ vcosel = '00' @ vcosel = '01' @ vcosel = '10' @ vcosel = '11'
Note: When TC1920 starts-up with the PLL not bypassed, first user instructions are executed with the frequency defined by the VCO free-running frequency (fPLLBASE) and by the reset value of the PLL_CLC register (the K-divider and VCOSEL bitfields). It is software responsibility to initialize its own appropriate values in the bitfields in this register, before giving the command for the VCO to lock to the input frequency. For more information, see the Users Manual, System Units, System Control Unit chapter.
Data Sheet
55
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TC1920
Preliminary
5.0 ns
DN
4.0
fSYS = 100 MHz (K = 3) fSYS = 80 MHz (K = 3) fSYS = 60 MHz (K = 5) fSYS = 40 MHz (K = 7)
TC1920_pll_jitter
3.0
2.0
1.0
0.0
0 5 10 15 20 25 30 35
DN = Max. jitter P = Number of consecutive fSYS periods K = K-divider of PLL
P
Figure 21
Approximated Maximum Accumulated PLL Jitter
The following two formulas define the (absolute) approximate maximum value of jitter DN in [ns] dependent on the K-factor, the system clock frequency fSYS in [MHz], and the number P of consecutive fSYS periods. for P < 0.25x fSYS
DN [ns] = [( + 0.9) x fSYS x K
735
P fSYS x 0.25
+ 0.5 ] [1]
for P > 0.25x fSYS
DN [ns] = [
735 + 1.4 ] fSYS x K
[2]
With rising number P of clock cycles the maximum jitter increases linearly up to a specific value of P. Beyond this value of P the maximum accumulated jitter remains at a constant value.
Data Sheet
56
V 1.3, 2003-10
TC1920
Preliminary Timing for EBU_LMB Clock Outputs (Operating Conditions apply; CL = 50 pF) Parameter EBUCLK period EBUCLK high time EBUCLK low time EBUCLK rise time EBUCLK fall time BFCLK0 period BFCLK0 high time BFCLK0 low time BFCLK0 rise time BFCLK0 fall time Symbol Limits min. max. - - - 2.5 2.5 - - - 3.5 2.5 ns ns ns ns ns ns ns ns ns ns 10 4.5 3 - - 20 9 9 - - Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10
CC CC CC CC CC CC CC CC CC CC
t 1 (t 6 )
EBU CLK/ BFC LK 0 0 .5 V D D 0 .9 V D D 0 .1 V D D
t 2 (t 7 )
t 3 (t 8 )
t 5 (t 1 0 )
t 4 (t 9 )
M C T 0 4 88 4
Figure 22
EBU_LMB Clock Output Timing
Data Sheet
57
V 1.3, 2003-10
TC1920
Preliminary Timing for SDRAM Access Signals (Operating Conditions apply; CL = 50 pF) Parameter CKE high from EBUCLK CKE low from EBUCLK A(23:0) output valid from EBUCLK A(23:0) output hold from EBUCLK CS(6:0) low from EBUCLK CS(6:0) high from EBUCLK RAS low from EBUCLK RAS high from EBUCLK CAS low from EBUCLK CAS high from EBUCLK RD/WR low from EBUCLK RD/WR high from EBUCLK BC(3:0) low from EBUCLK BC(3:0) high from EBUCLK AD(31:0) output valid from EBUCLK AD(31:0) output hold from EBUCLK AD(31:0) input setup to EBUCLK AD(31:0) input hold from EBUCLK Symbol Limits min. max. 7.0 7.0 7.0 7.0 7.0 7.0 7.0 7.7 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17
CC CC 2.0 CC CC 2.0 CC CC 2.0 CC CC 2.0 CC CC 2.0 CC CC 2.0 CC CC 2.0 CC CC 2.0 SR 2.0
t18 SR 4.0
Data Sheet
58
V 1.3, 2003-10
TC1920
Preliminary
Write Access: EBUCLK
t1
CKE A(23:0)
t3
Row
t4
Column
t5
CSx
t6 t8
RAS
t7
CAS
t10 t9
t12 t14
RD/WR
t11
BC(3:0)
t13
AD(31:0)
Data (0) Data (n-1)
t15
Read Access: EBUCLK
t16
t2
CKE A(23:0) Row
t3
Column
t4 t6
CSx RAS CAS RD/WR BC(3:0)
t9
t10
t13
t14 t17 t18
Data (n-1)
MCT05319
AD(31:0)
Data (0)
Figure 23
SDRAM Access Timing
Data Sheet
59
V 1.3, 2003-10
TC1920
Preliminary Timing for Burst Flash Access Signals Operating Conditions apply; CL = 50 pF) Parameter A(23:0) output valid from BFCLK0 A(23:0) output hold from BFCLK0 CS(6:0) low from BFCLK0 ADV low from BFCLK0 ADV high from BFCLK0 BAA low from BFCLK0 BAA high from BFCLK0 RD low from BFCLK0 AD(31:0) input setup to BFCLK0 AD(31:0) input hold from BFCLK0 Symbol Limits min. max. 11.0 - 9.0 10.0 - 10.0 - 10.0 - - ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t5 t6 t7 t8 t9 t11 t12
CC - CC 0.0 CC - CC - CC 3.0 CC - CC 3.0 CC - SR 6.0 SR 3.0
Data Sheet
60
V 1.3, 2003-10
TC1920
Preliminary
BFCLK0
t1
A[23:0]
Address Valid
t2 t6
t5
ADV
t3
CSx
t9
RD
t7
BAA
t8
t11 t12
D[31:0]
Valid Valid
Note: Between the end of the Address Phase (ADV goes high) and the beginning of the Command Phase (RD goes low) several cycles of Command Delay Phase can be inserted.
mct04889_mod_la
Figure 24
Burst Flash Access Timing (Instruction Read)
Data Sheet
61
V 1.3, 2003-10
TC1920
Preliminary Timing for Demultiplexed Access Signals1) (Operating Conditions apply; CL = 50 pF) Parameter ALE high from EBUCLK ALE low from EBUCLK A(23:0) output valid from EBUCLK A(23:0) output hold from EBUCLK CS(6:0) low from EBUCLK CS(6:0) high from EBUCLK MR/W low from EBUCLK MR/W high from EBUCLK RMW low from EBUCLK RMW high from EBUCLK RD low from EBUCLK RD high from EBUCLK RD/WR low from EBUCLK RD/WR high from EBUCLK CMDELAY input setup to EBUCLK CMDELAY hold from EBUCLK WAIT input setup to EBUCLK WAIT hold from EBUCLK BC(3:0) low from EBUCLK BC(3:0) high from EBUCLK AD(31:0) output valid from EBUCLK AD(31:0) output hold from EBUCLK AD(31:0) input setup to EBUCLK AD(31:0) input hold from EBUCLK Symbol Limits min. max. 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - - - - 8.0 - 8.0 - - - Uni t ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22 t23 t24
CC - CC 2.0 CC - CC 2.0 CC - CC 2.0 CC - CC 2.0 CC - CC 1.0 CC - CC 0.0 CC - CC 2.0 SR 4.0 SR 3.0 SR 4.0 SR 3.0 CC - CC 2.0 CC - CC 0.0 SR 4.0 SR 4.0
1)
It is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase length according to the particular asynchronous memory/peripheral device specification.
Data Sheet
62
V 1.3, 2003-10
TC1920
Preliminary
EBUCLK
t1
ALE
t2 t3
A(23:0) Address
t4
t5
CSx
t6
t7
MR/W
t14
RD/WR
t16 t15 t13
CMDELAY
t18 t17
WAIT
t20 t19 t19 t20
BC(3:0)
t21
AD(31:0) Data Out
t22
MCT05320
Figure 25
Demultiplexed Write Access
Data Sheet
63
V 1.3, 2003-10
TC1920
Preliminary
EBUCLK
t1
ALE
t2 t3
A(23:0) Address
t4
t6
CSx
t5
MR/W
t8
RMW
t10
t9
RD
t12 t16 t15 t11
CMDELAY
t18 t17
WAIT
t19
BC(3:0)
t19
t20
t23
AD(31:0) Note: RMW signal is available only during Read-Modify-Write Access. Data
t24
MCT05321
Figure 26
Demultiplexed Read Access
Data Sheet
64
V 1.3, 2003-10
TC1920
Preliminary Timing for Multiplexed Access Signals1) (Operating Conditions apply; CL = 50 pF) Parameter ALE high from EBUCLK ALE low from EBUCLK AD(31:0) output valid from EBUCLK AD(31:0) output hold from EBUCLK AD(31:0) input setup to EBUCLK AD(31:0) input hold from EBUCLK CS(6:0) low from EBUCLK CS(6:0) high from EBUCLK MR/W low from EBUCLK MR/W high from EBUCLK RMW low from EBUCLK RMW high from EBUCLK RD/WR low from EBUCLK RD/WR high from EBUCLK RD low from EBUCLK RD high from EBUCLK CMDELAY input setup to EBUCLK CMDELAY hold from EBUCLK WAIT input setup to EBUCLK WAIT hold from EBUCLK BC(3:0) low from EBUCLK BC(3:0) high from EBUCLK Symbol Limits min. max. 8.0 - 8.0 - - - 8.0 - 8.0 - 8.0 - 8.0 - 8.0 - - - - - 8.0 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 t20 t21 t22
CC - CC 2.0 CC - CC 0.0 SR 4.0 SR 4.0 CC - CC 1.0 CC - CC 2.0 CC - CC 1.0 CC - CC 2.0 CC - CC 0.0 SR 4.0 SR 3.0 SR 4.0 SR 3.0 CC - CC 2.0
1)
It is user responsibility to program an appropriate whole number of clock cycles to generate the correct phase length according to the particular asynchronous memory/peripheral device specification.
Data Sheet
65
V 1.3, 2003-10
TC1920
Preliminary
EBUCLK
t1
ALE
t2 t3
AD(31:0) Address Data
t4
t7
CSx
t4 t3
t8
t9
MR/W
t14
RD/WR
t18 t17 t13 t20 t19
CMDELAY
WAIT
t22 t21 t21 t22
BC(3:0)
MCT05322
Figure 27
Multiplexed Write Access
Data Sheet
66
V 1.3, 2003-10
TC1920
Preliminary
EBUCLK
t1
ALE
t2 t3
AD(31:0) Address
t5 t6
Data
t4
CSx
t8
t7
MR/W
t10
RMW
t12
t11
RD
t16 t18 t17 t15
CMDELAY
t20 t19
WAIT
t21
BC(3:0)
t21
t22
Note: RMW signal is only available during Read-Modify-Write Access.
MCT05323
Figure 28
Multiplexed Read Access
Data Sheet
67
V 1.3, 2003-10
TC1920
Preliminary Timing for External Bus Arbitration Signals (Operating Conditions apply; CL = 50 pF) Parameter HOLD input setup to EBUCLK HOLD input hold from EBUCLK HLDA low from EBUCLK HLDA high from EBUCLK HLDA input setup to EBUCLK HLDA input hold from EBUCLK BREQ low from EBUCLK BREQ high from EBUCLK Symbol Limits min. max. - - 10.0 9.0 - - 10.0 9.0 ns ns ns ns ns ns ns ns Unit
t1 t2 t3 t4 t5 t6 t7 t8
SR 6.0 SR 8.0 CC - CC - SR 8.0 SR 8.0 CC - CC -
Note: The signals HOLD, HLDA and BREQ are alternate function of the CS5, CS6 and CSOVL Pins.
Data Sheet
68
V 1.3, 2003-10
TC1920
Preliminary
External M aster M ode EBU C LK
t1
H OLD
t2
t4
H LDA
t3
BREQ
t8
t7
External S lave M ode EBU C LK
t7
BREQ
t8
t5
H LDA
t6
t1
H OLD
t2
M C T 05324_m od
Figure 29
External Bus Arbitration Timing
Data Sheet
69
V 1.3, 2003-10
TC1920
Preliminary SSC Master Mode Timing (Operating Conditions apply; CL = 50 pF) Parameter SCLK period MTSR low/high from SCLK edge MRST setup to SCLK edge MRST hold from SCLK edge Symbol min. tSCLK t5 t6 t7 CC CC SR SR 40 15 15 2.0 Limit Values max. ns ns ns ns Unit
tSCL K
SCLK
(C O N .P O ,C O N .P H =0 0 o r 1 1 )
0 .5 V D D
0 .9 V D D 0 .1 V D D
SCLK
(C O N .P O ,C O N .P H =0 1 o r 1 0 )
0 .5 V D D
0 .9 V D D 0 .1 V D D
t5
M TSR
S tate n -1 S ta te n S ta te n +1
t6
M RST
t7
D a ta va lid
M C T0 4 88 5 m o d
D a ta va lid
Figure 30
SSC Master Mode Timing
Data Sheet
70
V 1.3, 2003-10
TC1920
Preliminary Package Outlines
Figure 31
LBGA-260 Package
You can find all of our packages, sorts of packing and other in our Infineon Internet Page "Products": http://www.infineon.com/products *
Data Sheet
71
V 1.3, 2003-10
TC1920
Preliminary
Data Sheet
72
V 1.3, 2003-10
((73))
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